Tag Archives: VHDL

Adding SPI support to the BrainF interpreter

While at Chicago’s O’Hare airport, waiting for my connecting flight to Reno, I had a bit of time to start coding on my BrainF interpreter again — once I had found an outlet, that is1. My goal was to add … Continue reading

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Improving the BrainF interpreter

As I wrote in a previous post, I wrote a BrainF interpreter in VHDL over a week-end. I decided to improve it a bit.

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Writing a BrainF interpreter … in VHDL

I’ve written parsers and interpreters before, but usually in C++ or, if I was feeling like doing all of the hard work myself, in C.

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